MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 752

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Modular Input/Output Subsystem (MIOS14)
17.8.1
17-20
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•
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Counter Clock
Programmable 16-bit modulus up-counter with a built-in programmable 8-bit prescaler clocked by
MCPSM
Maximum increment frequency of the counter:
— clocked by the internal MCPSM output: f
— clocked by the external signal: f
Flag setting and possible interrupt generation on overflow of the up-counter register
Modulus Value
Two’s Complement
MMCSM Features
signal (MMCnL)
signal (MMCnC)
Modulus Load
Clock input
0xFFFF
PINC
PINC
PINL
8-bit Prescale
Mod.Register
EDGN
CP7 - CP0
8-bit Clock
Prescaler
Detect
Edge
Figure 17-11. MMCSM Modulus Up-Counter
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 17-10. MMCSM Block Diagram
EDGP
Edge
Detect
CLS0
SYS
Select
Clock
/ 4
CLS1
Enable
MMCSMCNT
Clock
MMCSMML
Load
SYS
FREN
Control
Load
/ 2
Clock
Counter Reload
16-bit Up-Counter Reg.
16-bit Counter Bus
16-bit Modulus
Latch Reg.
Overflow
MIOB
Request Bus
Flag
Freescale Semiconductor