MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 324

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Clocks and Power Control
8.8.2
The MPC561/MPC563 provides a wide range of possibilities for power supply connections.
illustrates the different power supply sources for each of the basic units on the chip.
8.8.2.1
This supplies the final output stage of the 2.6-V pad output drivers.
8.8.2.2
This supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-V pad output
drivers.
8.8.2.3
VDD powers the internal logic of the MPC561/MPC563, nominally 2.6V.
8.8.2.4
The charge pump and the VCO of the SPLL are fed by a separate 2.6-V power supply (VDDSYN) in order
to improve noise immunity and achieve a high stability in its output frequency. VSSSYN provides an
isolated ground reference for the PLL.
8.8.2.5
The oscillator, time base counter, decrementer, periodic interrupt timer and the real-time clock are fed by
the KAPWR rail. This allows the external power supply unit to disconnect all other sub-units of the MCU
in low-power deep-sleep mode. The TEXP pin (fed by the same rail) can be used by the external power
supply unit to switch between sources. The IRQ[6:7]/MODCK[2:3], IRQ5/MODCK1, XTAL, EXTAL,
EXTCLK, PORESET
Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR.
8.8.2.6
VDDA supplies power to the analog subsystems of the QADC64E_A and QADC64E_B modules; it is
nominally 5.0 V. VSSA is the ground reference for the analog subsystems.
8.8.2.7
VFLASH supplies the UC3F normal operating voltage. It is nominally 5.0 V. The MPC561 has no
VFLASH signal.
8.8.2.8
VDDF provides internal core voltage to the UC3F Flash module; it should be a nominal 2.6V. VSSF
provides an isolated ground for the UC3F Flash module. The MPC561 has no VDDF or VSSF signal.
8-22
Chip Power Structure
NVDDL
QVDDL
VDD
VDDSYN, VSSSYN
KAPWR
VDDA, VSSA
VFLASH
VDDF, VSSF
,
HRESET, SRESET, and RSTCONF/TEXP input pins are powered by KAPWR.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
Figure 8-11

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