MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1369

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Note: All delays are in system clock periods.
Freescale Semiconductor
1
2
3
MMCSM Enable to counter bus increment
(MIN)
MMCSM Enable to counter bus increment
(MAX)
Minimum output resolution depends on MMCSM and MCPSM prescaler settings.
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MMCSMSCR_CP[7:0] =0xFF.
The exact timing from MMCSM enable to the pin being set depends on the timing of the MMCSMSCR register write
and the MCPSM VS_PCLK. The MMCSM enable is taken to mean the MMCSMSCR_CLS[1:0] being written to
2‘b11.
MMCSM clock pin
Counter bus[15:0]
3
3
MMCSM pin
Figure G-51. MMCSM Minimum Input Pin (Either Load or Clock) Timing Diagram
f
SYS
Figure G-52. MMCSM Clock Pin to Counter Bus Increment Timing Diagram
Characteristic
f
f
SYS
is the internal system clock for the IMB3 bus.
SYS
Table G-25. MMCSM Timing Characteristics (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
t
PCCB
t
PPER
min
A
Symbol
t
t
NOTE
MCME
MCME
A+1
t
PLO
min
4 + MCPSMSCR_PSL*
(255 - MMCSMSCR_CP)
4 + MCPSMSCR_PSL * (255 - MMCSMSCR_CP)
+ (MCPSMSCR_PSL - 1)
Min
t
min
PHI
66-MHz Electrical Characteristics
3
3
Max
G-63