MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 30

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

23.4.4
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.6
23.4.6.1
23.4.6.2
23.4.6.3
23.4.6.4
23.4.6.5
23.4.6.6
23.4.6.7
23.4.6.8
23.4.6.9
23.4.6.10
23.4.6.11
23.5
23.5.1
23.6
23.6.1
23.6.2
23.6.3
23.6.4
23.6.5
23.6.6
23.6.7
23.6.8
23.6.9
23.6.10
23.6.11
23.6.12
23.6.13
24.1
24.1.1
24.2
24.2.1
Freescale Semiconductor
Paragraph
Number
Software Monitor Debugger Support ......................................................................... 23-38
Development Support Registers ................................................................................. 23-39
Features Summary ........................................................................................................ 24-1
Modes of Operation ...................................................................................................... 24-3
Development Serial Data Out ................................................................................. 23-29
Freeze Signal ........................................................................................................... 23-29
Development Port Registers ................................................................................... 23-30
Freeze Indication ..................................................................................................... 23-38
Register Protection .................................................................................................. 23-40
Comparator A–D Value Registers (CMPA–CMPD) .............................................. 23-41
Exception Cause Register (ECR) ............................................................................ 23-41
Debug Enable Register (DER) ................................................................................ 23-43
Breakpoint Counter A Value and Control Register ................................................ 23-45
Breakpoint Counter B Value and Control Register ................................................ 23-46
Comparator E–F Value Registers (CMPE–CMPF) ................................................ 23-46
Comparator G–H Value Registers (CMPG–CMPH) .............................................. 23-47
L-Bus Support Control Register 1 .......................................................................... 23-47
L-Bus Support Control Register 2 .......................................................................... 23-48
I-Bus Support Control Register (ICTRL) ............................................................... 23-51
Breakpoint Address Register (BAR) ...................................................................... 23-53
Development Port Data Register (DPDR) .............................................................. 23-53
Functional Block Diagram ........................................................................................ 24-2
Reset Configuration .................................................................................................. 24-3
SGPIO6/FRZ/PTR Signal ................................................................................... 23-30
IWP[0:1]/VFLS[0:1] Signals .............................................................................. 23-30
VFLS[0:1]/MPIO32B[3:4] Signals ................................................................... 23-30
Development Port Shift Register ........................................................................ 23-30
Trap Enable Control Register ............................................................................. 23-30
Development Port Registers Decode .................................................................. 23-31
Development Port Serial Communications — Clock Mode Selection ............... 23-31
Development Port Serial Communications — Trap Enable Mode .................... 23-33
Serial Data into Development Port — Trap Enable Mode ................................. 23-33
Serial Data Out of Development Port — Trap Enable Mode ............................. 23-34
Development Port Serial Communications — Debug Mode ............................. 23-35
Serial Data Into Development Port ..................................................................... 23-35
Serial Data Out of Development Port ................................................................. 23-36
Fast Download Procedure ................................................................................... 23-37
MPC561/MPC563 Reference Manual, Rev. 1.2
READI Module
Contents
Chapter 24
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