MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 365

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Freescale Semiconductor
2. Receive Bus Grant (BG) from Arbiter
4. Assert Transfer Start (TS)
6. Drive BURST Asserted
1. Request Bus (BR)
3. Assert Bus Busy (BB) if No Other Master is Driving
5. Drive Address and Attributes
7. MTS Asserted (from MPC500 Device)
Negate Burst Data in Progress (BDIP)
ADDR[28:29] mod 4 =?
Stop Driving Data
External Master
Assert BDIP
= 2
Drive Data
Drive Data
Assert BDIP
Drive Data
= 3
= 1
Drive data
Assert BDIP
= 0
MPC561/MPC563 Reference Manual, Rev. 1.2
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Receive Address
BDIP Asserted
BDIP Asserted
BDIP Asserted
BDIP Asserted
Sample Data
Sample Data
Sample Data
Sample Data
Slave
Yes
Yes
Yes
Yes
No
No
No
No
External Bus Interface
Don’t Sample
Next Data
Don’t Sample
Next Data
Don’t Sample
Next Data
Don’t Sample
Next Data
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