MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 593

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

14.4.7
The QADC64E module communicates with other microcontroller modules via the IMB3. The QADC64E
bus interface unit (BIU) coordinates IMB3 activity with internal QADC64E bus activity. This section
describes the operation of the BIU, IMB3 read/write accesses to QADC64E memory locations, module
configuration, and general-purpose I/O operation.
14.4.7.1
The BIU is designed to act as a slave device on the IMB3. The BIU has the following functions: to respond
with the appropriate bus cycle termination, and to supply IMB3 interface timing to all internal module
signals.
BIU components consist of
14.4.7.2
The QADC64E supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. Coherency of
results read (ensuring that all results read were taken consecutively in one scan) is not guaranteed. For
example, if a read of two consecutive 16-bit locations in a result area is made, the QADC64E could change
one 16-bit location in the result area between the bus cycles. There is no holding register for the second
16-bit location. All read and write accesses that require more than one 16-bit access to complete occur as
two or more independent bus cycles. Depending on bus master protocol, these accesses could include
misaligned and 32-bit accesses.
Figure 14-24
paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit
accesses.
Freescale Semiconductor
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IMB3 buffers
Address match and module select logic
The BIU state machine
Clock prescaler logic
Data bus routing logic
Interface to the internal module data bus
Configuration and Control Using the IMB3 Interface
QADC64E Bus Interface Unit
QADC64E Bus Accessing
shows the three bus cycles which are implemented by the QADC64E. The following
Normal accesses from the IMB3 to the QADC64E require two clocks.
However, if the CPU tries to access table locations while the QADC64E is
accessing them, the QADC64E produces IMB3 wait states. From one to
four IMB3 wait states may be inserted by the QADC64E in the process of
reading and writing.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
QADC64E Enhanced Mode Operation
14-51