M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 391

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
24. Programmable I/O Ports
24.1 Port Pi Direction Register (PDi Register, i=0 to 15)
24.2 Port Pi Register (Pi Register, i=0 to 15)
24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9)
24.4 Function Select Register Bk (PSLk Register) (k=0 to 3)
e
E
3
. v
J
2
0
87 programmable I/O ports from P0 to P10 (excluding P8
programmable I/O ports from P0 to P15 (excluding P8
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P8
allowed. The P8_5 bit in the P8 register indicates an NMI input level since P8
Figures 24.1 to 24.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
function. Refer to 7. Bus when used as the bus control pin.
The registers, described below, are associated with the programmable I/O ports.
Figure 24.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
In memory expansion and microprocessor mode, pins being used as bus control pins (A0 to A
D
HOLD, ALE/RAS, and RDY) cannot be controlled by the PDi register. No bits controlling P8
in the direction registers .
Figure 24.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
In memory expansion and microprocessor mode, pins being used as bus control pins (A
D
HOLD, ALE/RAS, and RDY) cannot be controlled by the Pi register.
Figures 24.7 to 24.11 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph-
eral function output (excluding DA0 and DA1.)
Tables 24.3 to 24.12 list peripheral function output control settings for each pin.
When multiple peripheral function outputs are assigned to a pin, set the PSLk (k=0 to 3) and PSC registers
to select which function is used.
Figures 24.12 and 24.13 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 24.9 Analog Input and Other Peripheral Function Input for the PSL3_3 to PSL3_6 bits in the
PSL3 register.
1
C
_________
_________
9
3 .
B
15
15
8 /
0
1
, MA
, MA
3
0
3
J
G
4
a
0 -
o r
n
0
0
3 .
1
u
to MA
to MA
, 1
3
p
1
_______
_______
2
(
M
0
0
3
6
12
12
2
C
, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLK
, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLK
Page 366
8 /
_______
_______
, 3
_______
_______
M
3
2
_______
_______
C
f o
8 /
4
3
8
) T
________ ______ _________
________ ______ _________
8
________ _______
________ _______
______
5
) are in the 144-pin package. The direction registers
5
5
) are available in the 100-pin package and 123
is an input port and no pull-up for this port is
_____ ______
_____ ______
5
shares pins with NMI.
24. Programmable I/O Port
0
OUT
to A
OUT
5
, HLDA/ALE,
, HLDA/ALE,
22
22
are provided
_________
_________
, A
, A
_____
_____
______
23
23
, D
, D
0
0
to
to