M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 318

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
Figure 21.36 G0ERC to G1ERC Registers
0
1
C
9
3 .
B
8 /
0
1
3
0
Group i SI/O Expansion Receive Control Register (i=0,1)
b7
3
J
G
NOTES:
4
a
0 -
n
o r
b6
1. The GiERC register is used in special communication mode or HDLC data processing mode.
2. When the ACRC bit in the GiEMR register is set to "1" (CRC reset function used), set the CMP3E bit
3 .
1
u
, 1
3
b5
to "1".
Set to "0010 0000
p
1
2
(
M
b4
0
0
3
6
b3
2
C
b2
8 /
Page 293
, 3
b1
M
b0
2
3
" in clock synchronous serial I/O mode. Do not use in UART mode.
2
CMP1E
CMP2E
RCRCE
CMP0E
CMP3E
C
RSHTE
RBSF0
RBSF1
Symbol
f o
8 /
Bit
4
Symbol
G0ERC,G1ERC
3
8
) T
8
Data Compare
Function 2
Select Bit
Data Compare
Function 3
Select Bit
Receive CRC
Enable Bit
Receive Shift
Operation
Enable Bit
Receive Bit
Stuffing
"1" Delete
Select Bit
Receive Bit
Stuffing
"0" Delete
Select Bit
Data Compare
Function 0
Select Bit
Data Compare
Function 1
Select Bit
Bit Name
Address
00FD
0 : The GiDR register (transmit data register) is
1 : The GiDR register is compared with the
0 : The GiDR register (transmit data register) is
1 : The GiDR register is compared with the
0 : The GiDR register (transmit data register) is
1 : The GiDR register is compared with the
0 : Not used
1 : Used
0 : Disables receive shift operation
1 : Enables receive shift operation
0 : "1" is not deleted
1 : "1" is deleted
0 : "0" is not deleted
1 : "0" is deleted
0 : The GiDR register (transmit data register) is
1 : The GiDR register is compared with the
21. Intelligent I/O (Group 0, 1 Communication Function)
16
not compared with the GiCMP1 register
GiCMP1 register
not compared with the GiCMP2 register
GiCMP2 register
not compared with the GiCMP3 register
GiCMP3 register
not compared with the GiCMP0 register
GiCMP0 register
, 013D
16
Function
(2)
After Reset
00
16
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW