M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 224

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 16.20 UiRB Register Transfer and Interrupt Timings
Table 16.15 Pin Settings in I
2
0
P6
P6
P6
P6
1
9
C
3 .
B
Port
8 /
2
3
6
7
0
1
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
(3) When IICM2 is set to "1" (UART transmit or receive interrupt) and CKPH is set to "0"
3
0
(2) When IICM2 is set to "0" and CKPH is set to "1" (clock delay)
SCLi
SDAi
SCLi
SDAi
SCLi
SDAi
SCLi
SDAi
(4) When IICM2 is set to "1" and CKPH is set to "1"
3
J
G
4
a
i=0 to 4
IICM2 : Bit in the UiSMR2 register
CKPH : Bit in the UiSMR3 regiser
The above timing applies to the following setting :
• CKDIR bit in the UiMR register = 1 (select slave)
0 -
n
o r
3 .
1
u
, 1
3
p
SCL0 output
SCL0 input
SDA0 output
SDA0 input
SCL1 output
SCL1 input
SDA1 output
SDA1 input
1
2
(
1st
1st
1st
bit
bit
bit
M
1st
0
bit
D
D
D
D
0
3
7
7
7
Function
7
6
2
C
2nd
2nd
2nd
bit
2nd
bit
bit
bit
D
Page 199
8 /
D
D
D
6
6
6
6
, 3
3rd
3rd
3rd
bit
3rd
bit
bit
M
bit
D
D
D
D
5
3
5
5
5
2
C
4th
4th
4th
bit
bit
bit
f o
4th
Data is transferred to the UiRB register.
bit
2
D
D
D
Data is transferred to the UiRB register
8 /
D
C Mode (1)
4
4
4
4
b15
4
3
8
PS0_2=1
PS0_2=0
PS0_3=1
PS0_3=0
PS0_6=1
PS0_6=0
PS0_7=1
PS0_7=0
) T
8
•••
5th
5th
5th
bit
bit
bit
5th
PS0 Register
bit
D
D
D
b9
Contents of the UiRB register
D
3
3
3
3
D
b8
0
6th
6th
6th
bit
bit
bit
6th
b7
bit
D
D
D
D
D
Data is transferred to the UiRB register
2
2
2
Data is transferred to the UiRB register
2
7
Receive interrupt
(DMA request)
D
Receive interrupt
(DMA request)
6
7th
7th
7th
bit
bit
bit
7th
bit
D
D
D
D
D
5
1
1
1
D
1
4
D
8th
8th
8th
bit
bit
bit
8th
3
bit
ACK interrupt (DMA
request) or NACK interrupt
ACK interrupt (DMA
request) or NACK interrupt
PSL0_2=0
-
-
-
PSL0_6=0
-
-
-
D
D
D
D
D
0
2
0
0
0
PSL0 Register
D
b0
1
9th
bit
9th
9th
bit
bit
9th
D
bit
D
D
D
Setting
8
8
8
Transmit interrupt
b15
b15
8
Data is transferred to the UiRB register.
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
Transmit interrupt
•••
•••
b9
b9
Contents of the UiRB register
Contents of the UiRB register
D
D
b8
b8
8
0
D
b7
b7
7
D
D
6
7
b15
b15
D
D
5
6
D
-
PD6_2=0
-
PD6_3=0
-
PD6_6=0
-
PD6_7=0
•••
•••
D
4
5
b9
Contents of the UiRB register
Contents of the UiRB register
D
b9
D
3
4
PD6 Register
D
D
D
b8
b8
D
8
8
2
3
D
D
b7
b7
D
D
16. Serial I/O (Special Function)
7
7
1
2
D
D
D
D
b0
b0
6
6
0
1
D
D
5
5
D
D
4
4
D
D
3
3
D
D
2
2
D
D
1
1
D
D
b0
b0
0
0