M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 345

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NOTES:
Table 21.41 Clock Synchronous Serial I/O Mode (Group 3)
9 0
C
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Error Detection
Selectable Function
21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3)
Transfer Data Format
. 1
1. The transfer clock must be f
2. Transmit interrupt request is generated when the TE bit is set to "1". Set the interrupt-associated
3. When an overrun error occurs, the G3RB register is indeterminate.
8 /
B
In 8-bit or 16-bit clock synchronous serial I/O mode, data is transmitted and received using the transfer
clock. When the internal clock is selected as the transfer clock, the channel 0 and channel 2 waveform
generation functions generate the transfer clock. ISTxD3, ISCLK3 and ISRxD3 share pins with OUTC3
to OUTC3
Table 21.41 lists specifications of clock synchronous serial I/O mode. Table 21.42 lists registers to be
used and their settings. Tables 21.43 and 21.44 list pin settings. Figure 21.50 and 21.51 shows an
example of transmit and receive operation.
1 3
0
3
registers after setting the TE bit.
3 0
G
J
- 4
n a
o r
1 0
3 .
u
Item
p
, 1
1 3
(
2
0 2
M
(1)
and are available in the 144-pin package only.
3
6 0
2
C
8 /
Page 320
, 3
(2)
M
3
2
• Transfer data :
• When the CKDIR bit in the G3MR register is set to "0" (internal clock) :
• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK3 pin
Set registers associated with the waveform generation function and the G3MR register.
• Set the TE bit in the G3CR register to "1" (transmit enable)
• Set the TI bit in the G3CR register to "0" (data in the G3TB register)
Set registers associated with the waveform generation function and the G3MR register.
• Set the RE bit in the G3CR register to "1" (receive enable)
• Set theTE bit to "1" (transmit enable)
• Set the TI bit to "0" (data in the G3TB register)
• While transmitting, one of the following conditions can be selected to set the
_
_
• While receiving, the following condition can be selected to set the SIO3RR bit in the
• Overrun error
• LSB first/MSB first
• ISTxD3 and ISRxD3 I/O polarity inverse
C
SIO3TR bit in the IIO10IR register to "1" (see Figure 10.14) :
15 transfer clock cycles after data transmission starts in 16-bit clock synchronous
serial I/O mode (set the DLS bit in the G3MR register to "0"), or
7 transfer clock cycles after data transmission starts in 8-bit clock clock synchronous
serial I/O mode (set the DLS bit to "1").
IIO9IR register to "1" (see Figure 10.14) :
serial I/O mode, or
f o
15.5 transfer clock cycles after data transmission starts in 16-bit clock synchronous
Select either bit 0 or bit 7 to transmit/receive data
ISTxD3 pin output level and ISRxD3 pin input level are inversed
7.5 transfer clock cycles after data transmission starts in 8-bit clock synchronous
serial I/O mode
next data is received before reading the G3RB register.
8 /
This error occurs in 16-bit clock synchronous serial I/O mode when the 15th bit of
_
Then, set as written below after waiting at least one transfer clock cycle.
Then, set as written below after waiting at least one transfer clock cycle.
the next data is received before reading the G3RB register.
This error occurs in 8-bit clock synchronous serial I/O mode when the 7th bit of the
When the IRS bit in the G3MR register is set to "0" (no data in the transmit buffer),
When the IRS bit is set to "1" (reception completed),
one transfer clock cycle after data transmission starts
4
3
delayed waveform output mode of the channel 2 waveform generation function.
The G3PO0 register determines the bit rate and the transfer clock is generated in phase-
BT3
8 8
) T
n : setting value of the G3PO0 register, 0001
divided by six or more.
(3)
21. Intelligent I/O (Group 3 Communication Function)
8 bits or 16 bits long
Specification
16
to FFFD
16
2(n+2)
f
BT3
0