M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 154

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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13.2 DMAC II Performance
13.3 Transfer Data
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3
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2
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• Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space
• Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
• Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired
13.1.3 Interrupt Control Register for the Peripheral Function
13.1.4 Relocatable Vector Table for the Peripheral Function
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11)
The DMAC II function is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II request is
activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These
peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral
function interrupt cannot be used.
When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "111
activated regardless of what state the I flag and IPL is in.
The DMAC II transfers 8-bit or 16-bit data.
When a 16-bit data is transferred to the destination address 0FFFF
10000
13.3.1 Memory-to-Memory Transfer
C
1
9
(Addresses 00000
memory location in a 64K-byte space.
3 .
B
8 /
For the peripheral function interrupt activating a DMAC II request, set the ILVL2 to ILVL0 bits to "111
(level 7).
Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt
activating a DMAC II request.
When using the chained transfer, the relocatable vector table must be located in the RAM.
When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE
register of the interrupt to "0".
Data transfer between any two memory locations can be:
• a transfer from a fixed address to another fixed address
• a transfer from a fixed address to a relocatable address
• a transfer from a relocatable address to a fixed address
• a transfer from a relocatable address to another relocatable address
When a relocatable address is selected, the DMAC II increments address, after a transfer, for the next
transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer
address is incremented by two.
When a source or destination address exceeds address 0FFFF
the source or destination address returns to address 000000
source and destination address at address 0FFFF
0
1
3
0
3
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4
16
a
o r
0 -
n
. The same transfer occurs when the source address is 0FFFF
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, 1
3
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0
0
3
6
2
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16
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, 3
to 0FFFF
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3
2
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4
16
3
8
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8
) to another desired memory location in the same space.
16
or below.
16
16
and continues incrementation. Maintain
as a result of address incrementation,
16
, it is transferred to 0FFFF
16
.
2
" (level 7), the DMAC II is
13. DMACII
16
and
2
"