M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 207

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.1 Clock Synchronous Serial I/O Mode
e
E
3
. v
J
Table 16.1 Clock Synchronous Serial I/O Mode Specifications
2
NOTES:
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmit Start Condition
Receive Start Condition
Interrupt Request Generation Timing • Transmit interrupt timing can be selected from the followings:
Error Detect
Selectable Function
0
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1
lists specifications of clock synchronous serial I/O mode. Table 16.2 lists registers to be used and settings.
Tables 16.3 to 16.5 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs
an "H" signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open
drain output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O
mode.
C
1
9
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
3 .
B
8 /
0
1
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on
the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
(interrupt requested).
3
0
3
J
G
4
a
Item
o r
0 -
n
3 .
u
1
, 1
3
p
1
(
2
M
0
0
3
6
2
C
8 /
Page 182
, 3
M
3
2
• Transfer data : 8 bits long
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
• Selected from the CTS function, RTS function or CTS/RTS function disabled
• To start transmitting, the following requirements must be met
• To start receiving, the following requirements must be met
• Receive interrupt timing
• Overrun error
This error occurs when the seventh bit of the next received data is read before reading
the UiRB register
• CLK polarity
• LSB first / MSB first
• Continuous receive mode
• Serial data logic inverse
C
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Apply an "L" signal to the CTSi pin when the CTS function is selected
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (transmit enable)
- Set the TI bit to "0" (data in the UiTB register)
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) :
- The UiIRS bit is set to "1" (transmission completed) :
Transferred data is output and input on either the rising edge or falling edge of the
Data is transmitted or received in either bit 0 or in bit 7
Data can be received simultaneously by reading the UiRB register
This function inverses transmitted or received data logically
f o
transfer clock
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
8 /
2(m+1)
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
when a data transfer from the UARTi transmit register is completed
4
3
8
f
) T
j
8
f
j
(3)
=f
1
, f
_______
8
, f
2
n
(1)
________
m :setting value of the UiBRG register 00
_______
Specification
16. Serial I/O (Clock Synchronous Serial I/O)
_______
_______ _______
(2)
:
(2)
:
16
to FF
16
.