M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 243

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.7 Special Mode 5 (SIM Mode)
e
E
. v
3
J
Table16.34 SIM Mode Specifications
0
2
NOTES:
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and the TxDi pin (i=0 to 4) can output an "L" signal when a parity error is detected.
Table 16.34 lists specifications of SIM mode. Table 16.35 lists registers to be used and register settings in
SIM mode. Tables 16.36 to 16.38 list the pin settings.
Transfer Clock
Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
Other Setting Items
Transmit Start Condition To start transmitting, the following requirements must be met:
Receive Start Condition To start receiving, the following requirements must be met:
Interrupt Request
Generation Timing
Error Detection
1
Transfer Data Format
9
C
3 .
B
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
8 /
0
1
0
3
"1" (interrupt requested).
3
J
G
4
a
Item
0 -
n
o r
3 .
1
u
, 1
3
p
1
2
(
M
0
0
3
6
2
C
Page 218
8 /
, 3
The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
f
Do not set the CKDIR bit to "1" (external clock selected)
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the TI bit in the UiC1 register to "0" (data being in the UiTB register)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Detect the start bit
Transmit interrupt timing
• The UiIRS bit is set to "1" (transmission is completed):
Receive interrupt timing
• Overrun error
• Framing error
• Parity error
• Error sum flag
• Transfer data: 8-bit UART mode
• One stop bit
• In direct format
• In inverse format
j
This error occurs when the number of "1" in parity bit and character bits differ from
/16(m+1)
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
This error occurs when the eighth bit of the next data is received before reading the UiRB register
when data transmission from the UARTi transfer register is completed
This error occurs when the number of the stop bit set is not detected
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs.
M
the number set.
Parity:
Data logic:
Transfer format: LSB first
Parity:
Data logic:
Transfer format: MSB first
3
2
C
f o
8 /
4
(1)
8
3
8
) T
f
j
(1)
= f
1
, f
Even
Direct
Odd
Inverse
8
, f
2n (2)
m : setting value of the UiBRG register
Specification
16. Serial I/O (Special Function)
00
16
to FF
16