M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 134

IC M32C/83 MCU FLASH 100LQFP

M30833FJGP#U5

Manufacturer Part Number
M30833FJGP#U5
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30833FJGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
Figure 10.14 IIO0IR to IIO11IR Registers
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
Interrupt Request Register
4
a
b7
BTiR
TMmjR
POijR
SIOiRR/SIOiTR
GmRIR/GmTOR
SRTmR
IEkR
CANkR
-
Bit Symbols for the Interrupt Request Register
0 -
n
o r
IIO10IR
Symbol
IIO11IR
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
3 .
1
u
b6
NOTES:
, 1
3
p
1
1. See table below for bit symbols.
2. Only "0" can be set (nothing is changed even if "1" is set).
2
b5
(
M
0
0
3
b4
Address
6
00AA
00AB
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
2
C
b3
: Intelligent I/O Group i Base Timer Interrupt Request Bit (i=0 to 3)
: Intelligent I/O Group m Time Measurement j Interrupt Request Bit (j=0 to 7)(m=0,1)
: Intelligent I/O Group i Waveform Generation Function j Interrupt Request Bit
: Intelligent I/O Group i Communication Function Interrupt Request Bit (RR:receive, TR:transmit)
: Intelligent I/O Group m HDLC Data Processing Function Interrupt Request Bit
: Intelligent I/O Group m Special Communication Function Interrupt Request Bit
: Intelligent I/O Group 2 IEBus Communication Function Interrupt Request Bit (k = 0 to 2)
: CAN Communication Function Interrupt Request Bit
: Reserved bit. Set to "0".
8 /
Page 109
(RIR:input to receive, TOR:input to transmit)
16
16
16
16
16
16
16
16
16
16
16
16
, 3
b2
M
b1
CAN0R
CAN1R
CAN2R
SRT0R
3
IE0R
IE1R
Bit 7
2
-
-
-
-
-
-
b0
C
f o
8 /
4
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
3
Symbol
8
) T
(b0)
SRT1R
8
Bit
IE2R
Bit 6
Symbol
IIO0IR to IIO11IR
-
-
-
-
-
-
-
-
-
-
SIO0RR
SIO0TR
SIO1RR
SIO1TR
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0 : Requests no interrupt
1 : Requests an interrupt
Bit 5
-
-
-
-
-
-
-
-
SIO2RR
SIO3RR
SIO2TR
SIO3TR
G0TOR
G1TOR
G0RIR
G1RIR
BT1R
BT0R
BT2R
BT3R
Bit 4
Address
See below
PO27R
PO32R
PO33R
PO34R
PO35R
PO36R
PO31R
PO30R
PO37R
Bit 3
-
-
-
Function
TM12R/PO12R
TM17R/PO17R
PO13R
PO14R
PO10R
PO21R
PO20R
PO22R
PO23R
PO24R
PO25R
PO26R
Bit 2
After Reset
0000 000X
2
TM00R/PO00R
TM04R/PO04R
TM05R/PO05R
TM16R/PO16R
TM01R/PO01R
TM11R/PO11R
TM02R
TM03R
TM06R
TM07R
PO15R
Bit 1
-
( Note 2)
10. Interrupts
Bit 0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-

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