M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 282

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
0
Figure 21.9 BTSR Register
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
Base Timer Start Register
b7
3 .
1
u
NOTES:
, 1
3
p
b6
1
1. Set registers as follows before using the intelligent I/O:
2. Use the following procedure to start base timers in multiple groups simultaneously (including groups
2
(
M
0
b5
When starting the base timers separately, set the BTiS bit to "0" before setting the BTS bit in the
GiBCR1 register.
1 and 2 cascaded connections). This procedure is not required when starting the base timers
individually.
The BTiS bit (i=0 to 3) allows the base timers in multiple groups to start counting simultaneously.
• Set the BCK1 to BCK0 bits and DIV4 to DIV0 bits in the GiBCR0 register (i=0 to 3) of the groups to
• After the BCK1 to BCK0 bits or DIV4 to DIV0 bits are changed, use the following procedure to
0
3
be started simultaneously, to the same value.
start the base timer twice.
6
2
b4
C
Page 257
8 /
(1) Set the G2BCR0 register to supply the clock to the group 2 base timer
(2) Set all BT0S to BT3S bits in the BTSR register to "0" (base timer reset)
(3) Set other registers associated with the intelligent I/O
(1) Set the BTiS bit in the BTSR register to "1" (base timer starts counting).
(2) Set the BTiS bit to "0" (base timer stops counting) after one f
b3
(3) After waiting at least one additional f
, 3
counting).
b2
M
b1
3
2
C
b0
f o
8 /
4
(b7 - b4)
3
Symbol
8
BT0S
BT1S
BT2S
BT3S
) T
8
Bit
Symbol
BTSR
Group 0 Base Timer
Start Bit
Group 1 Base Timer
Start Bit
Group 2 Base Timer
Start Bit
Group 3 Base Timer
Start Bit
(1, 2)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
0164
BTi
16
clock cycle, set the BTiS bit to "1" (base timer starts
0 : Base timer reset
1 : Base timer starts counting
0 : Base timer reset
1 : Base timer starts counting
0 : Base timer reset
1 : Base timer starts counting
0 : Base timer reset
1 : Base timer starts counting
After Reset
XXXX 0000
BTi
Function
clock cycle.
2
21. Intelligent I/O
RW
RW
RW
RW
RW