M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 225

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
. v
3
J
Figure 16.21 Start Condition or Stop Condition Detect
Table 16.16 Pin Settings (2)
Table 16.17 Pin Settings (3)
0
2
NOTES:
NOTES:
P7
P7
P9
P9
P9
P9
16.3.1 Detecting Start Condition and Stop Condition
1
9
C
3 .
B
Port
Port
The microcomputer detects either a start condition or stop condition. The start condition detect interrupt
is generated when the SCLi (i=0 to 4) pin is held high ("H") and the SDAi pin changes high ("H") to low
("L"). The stop condition detect interrupt is generated when the SCLi pin is held high ("H") and the SDAi
pin changes low ("L") to high ("H"). The start condition detect interrupt shares interrupt control registers
and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which
interrupt is requested.
1. P7
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
8 /
0 (1)
1 (1)
1
2
6
7
0
1
0
3
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction
to set the PD9 and PS3 registers.
3
J
G
4
a
0
0 -
n
o r
and P7
3 .
1
u
, 1
3
p
SCL3 output
SCL3 input
SDA3 output
SDA3 input
SDA4 output
SDA4 input
SCL4 output
SCL4 input
1
SDA2 output
SDA2 input
SCL2 output
SCL2 input
2
(
M
0
1
0
3
6
are ports for the N-channel open drain output.
Function
2
Function
C
Page 200
8 /
, 3
(Start condition)
(Stop condition)
i=0 to 4
NOTES:
M
3
1. These cycles are main clock generation frequency cycles (X
3 to 6 cycles < setup time
3 to 6 cycles < hold time
SCLi
SDAi
SDAi
2
C
f o
8 /
4
8
3
PS3_1=1
PS3_1=0
PS3_2=1
PS3_2=0
PS3_6=1
PS3_6=0
PS3_7=1
PS3_7=0
PS1_0=1
PS1_0=0
PS1_1=1
PS1_1=0
8
) T
PS3 Register
PS1 Register
(1)
(1)
(1)
PSL1_0=0
PSL1_1=0
PSL3_1=0
-
PSL3_2=0
-
-
-
PSL3_7=0
-
Setup time
-
-
PSL1 Register
PSL3 Register
Setting
Setting
Hold time
PSC_0=0
PSC_1=0
-
-
-
PD9_1=0
-
PD9_2=0
-
PD9_6=0
-
PD9_7=0
PSC Register
PD9 Register
16. Serial I/O (Special Function)
IN
).
(1)
-
PD7_0=0
PD7_1=0
PD7 Register