M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 329

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 21.28 HDLC Processing Mode Specifications (Continued)
9 0
Data Processing
Start Conditions
Interrupt Request
. 1
C
1. Set the CRCV bit and ACRC bit in the GiEMR register to "1".
2. The CRC calculation circuit is reset after the GiRCRC register stores CRC data.
3. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
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The following conditions are required to start transmit data processing:
During transmit data processing,
During received data processing,
The following conditions are required to start receive data processing:
C
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• The TE bit in the GiCR register is set to "1" (transmit enable)
• Data is written to the GiTB register
• The RE bit in the GiCR register is set to "1" (receive enable)
• Data is written to the GiRI register
(1) One of the following conditions can be selected to set the GiTOR bit in the interrupt
(2) When data, which is already converted to HDLC data, is transferred from the
(1) When data is transferred from the GiRI register to the GiRB register (reception
(2) When received data is transferred from the receive buffer of the GiRI register to
(3) When the GiTB register is compared to the GiCMPj register (j=0 to 3), the SRTiR
8 /
4
request register to "1" (interrupt request) (see Figure 10.14)
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When the IRS bit in the GiMR register is set to "0" (no data in the GiTB register)
and data is transferred from the GiTB register to the transmit register (transmit start)
the transmit register to the GiTO register is completed
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
completed), the GiRIR bit is set to "1" (See Figure 10.14)
the receive register, the GiRIR bit is set to "1"
bit is set to "1"
When the IRS bit is set to "1" (transmission completed) and data transfer from
21. Intelligent I/O (Group 0, 1 Communication Function)
Specification