DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 802

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
4. Bit rate
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
• Confirmation, H'06, (one byte): Confirmation of a new bit rate
• Response, H'06, (one byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 20.26.
(6)
The boot program will transfer the erasing program, and erase the user MATs and user boot MATs
in that order. On completion of this erasure, ACK will be returned and will enter the
programming/erasing state.
Rev. 6.00 Sep. 24, 2009 Page 754 of 928
REJ09B0099-0600
Confirmation H'06
Response
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register
(SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral
operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that
it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is
calculated using the following expression:
Transition to Programming/Erasing State
Error (%) = {[
H'06
Waiting for one-bit period
at the specified bit rate
Setting a new bit rate
Host
(N + 1) × B × 64 × 2
Figure 20.26 New Bit-Rate Selection Sequence
φ × 10
6
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
(2×n − 1)
Setting a new bit rate
H'06 (ACK)
] − 1} × 100
Setting a new bit rate
Boot program