DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 251

IC H8S/2506 MCU FLASH 176-LFBGA

DF2506BR26DV

Manufacturer Part Number
DF2506BR26DV
Description
IC H8S/2506 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2506BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2506BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• P13/TIOCD0/TCLKB
Notes: 1. For the setting of the TPU channel, see section 10, 16-Bit Timer Pulse Unit (TPU).
• P12/TIOCC0/TCLKA
Notes: 1. For the setting of the TPU channel, see section 10, 16-Bit Timer Pulse Unit (TPU).
TPU Channel 0 Setting*
P13DDR
Pin function
TPU Channel 0 Setting*
P12DDR
Pin function
The pin function is switched as shown below according to the combination of the TPU channel
0 setting, the TPSC2 to TPSC0 bits in TCR_0, TCR_1, or TCR_2, and the P13DDR bit.
The pin function is switched as shown below according to the combination of the TPU channel
0 setting, the TPSC2 to TPSC0 bits in TCR_0, TCR_1, TCR_2, TCR_3, TCR_4, or TCR_5,
and the P12DDR bit.
2. This pin functions as TIOCD0 input when TPU channel 0 timer operating mode is set to
3. This pin functions as TCLKB input when TPSC2 to TPSC0 are set to 101 in any of
2. This pin functions as TIOCC0 input when TPU channel 0 timer operating mode is set to
3. This pin functions as TCLKA input when TPSC2 to TPSC0 are set to 100 in any of
normal operation and IOD3 to IOD0 in TIORL_0 are set to 10xx.
TCR_0, TCR_1, and TCR_2. This pin also functions as TCLKB input when channel 1 or
5 is set to phase counting mode.
normal operation and IOC3 to IOC0 in TIORL_0 are set to 10xx.
TCR_0, TCR_1, TCR_2, TCR_3, TCR_4, and TCR_5. This pin also functions as
TCLKA input when channel 1 or 5 is set to phase counting mode.
1
1
TIOCD0 output
TIOCC0 output
Output
Output
TCLKB input*
TCLKA input*
P13 input
P12 input
Rev. 6.00 Sep. 24, 2009 Page 203 of 928
0
0
Input or Initial Value
Input or Initial Value
TIOCD0 input*
TIOCC0 input*
3
3
Section 9 I/O Ports
P13 output
P12 output
REJ09B0099-0600
2
2
1
1

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