DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 25

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.2 Input/Output Pins ............................................................................................................... 611
18.3 Register Descriptions ......................................................................................................... 611
18.4 Operation ........................................................................................................................... 637
18.5 Interrupts............................................................................................................................ 654
18.6 DTC Interface .................................................................................................................... 655
18.7 CAN Bus Interface............................................................................................................. 656
18.8 Usage Notes ....................................................................................................................... 656
18.3.1 Master Control Register (MCR) ........................................................................... 612
18.3.2 General Status Register (GSR) ............................................................................. 613
18.3.3 Bit Configuration Register (BCR) ........................................................................ 615
18.3.4 Mailbox Configuration Register (MBCR) ............................................................ 617
18.3.5 Transmit Wait Register (TXPR) ........................................................................... 618
18.3.6 Transmit Wait Cancel Register (TXCR)............................................................... 619
18.3.7 Transmit Acknowledge Register (TXACK) ......................................................... 620
18.3.8 Abort Acknowledge Register (ABACK) .............................................................. 621
18.3.9 Receive Complete Register (RXPR)..................................................................... 622
18.3.10 Remote Request Register (RFPR)......................................................................... 623
18.3.11 Interrupt Register (IRR)........................................................................................ 624
18.3.12 Mailbox Interrupt Mask Register (MBIMR)......................................................... 628
18.3.13 Interrupt Mask Register (IMR) ............................................................................. 628
18.3.14 Receive Error Counter (REC)............................................................................... 630
18.3.15 Transmit Error Counter (TEC).............................................................................. 630
18.3.16 Unread Message Status Register (UMSR)............................................................ 630
18.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)............................................ 631
18.3.18 Message Control (MC0 to MC15) ........................................................................ 634
18.3.19 Message Data (MD0 to MD15) ............................................................................ 636
18.4.1 Hardware and Software Resets ............................................................................. 637
18.4.2 Initialization after Hardware Reset ....................................................................... 637
18.4.3 Message Transmission .......................................................................................... 643
18.4.4 Message Reception ............................................................................................... 647
18.4.5 HCAN Sleep Mode............................................................................................... 651
18.4.6 HCAN Halt Mode................................................................................................. 653
18.8.1 Module Stop Mode Setting ................................................................................... 656
18.8.2 Reset ..................................................................................................................... 656
18.8.3 HCAN Sleep Mode............................................................................................... 657
18.8.4 Interrupts............................................................................................................... 657
18.8.5 Error Counters....................................................................................................... 657
18.8.6 Register Access..................................................................................................... 657
18.8.7 HCAN Medium-Speed Mode ............................................................................... 657
18.8.8 Register Hold in Standby Modes and Watch Mode.............................................. 657
Rev. 6.00 Sep. 24, 2009 Page xxiii of xlvi
REJ09B0099-0600