DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 606

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 558 of 928
REJ09B0099-0600
Bit
5
4
3
Bit Name
DEE
CKS1
RE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Receive Enable
Description
Broadcast Receive Error Interrupt Enable
Since the acknowledgement is not returned between the
master and slave units in broadcast reception, the master
unit cannot decide whether the slave unit is in the receive
enabled state. If this bit is set to 1, a reception error
interrupt occurs (note that there is not the corresponding bit
in the IEBus receive error flag register to this error) when
the receive buffer is not in the receive enabled state during
receiving the control field in broadcast reception (when the
RE bit is not set to 1 or the RxRDY flag is set.). At this
time, the master address is stored in IEMA1 and IEMA2.
The receive data is not stored in IERCTL.
While this bit is 0, a reception error interrupt does not occur
when the receive buffer is not in the receive enabled state,
and the reception stops and enters the wait state. The
master address is not saved.
0: A broadcast receive error is not generated up to the
1: A broadcast receive error is generated up to the control
Input Clock Select
Selects clock used by the IEB. See table 17.7.
Enables/disables IEB reception. This bit must be set at the
initial setting before frame reception. Changing this bit
before receiving the control field is valid, however,
changing this bit after receiving the control field is invalid
and the value before the change is validated.
0: Reception is disabled.
1: Reception is enabled.
control field.
field.