DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 168

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
• When the SLEEP instruction causes a transition to software standby mode or watch mode
6.3.5
While the break interrupt enable bit is set to 1, instruction execution in the following cases is one
state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
• When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
• When break interruption by instruction fetch is set, if the instruction to be executed
• When break interruption by instruction fetch is set, if the instruction to be executed
Rev. 6.00 Sep. 24, 2009 Page 120 of 928
REJ09B0099-0600
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break exception handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(B)).
ROM or RAM
RAM space, and that address is used for data access
immediately before the set instruction has one of the addressing modes shown below, and that
address indicates on-chip ROM or RAM
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
immediately before the set instruction is NOP or SLEEP, or has #xx, Rn as its addressing
mode, and that instruction is located in on-chip ROM or RAM
When Instruction Execution Is Delayed by One State
Figure 6.2 Operation in Power-Down Mode Transitions
Execution of instruction
after SLEEP instruction
PC break exception
handling execution
SLEEP instruction
execution
(A)
SLEEP instruction
respective mode
Transition to
execution
(B)