DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 641

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2. If data is received up to the message length field, a receive start detection (RxS) interrupt
3. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI
4. Similarly, the data field reception and load are repeated.
5. When the last data is received, the DTC completes the data transfer for the specified number of
6. When the DTC transfer has been completed, an RxRDY interrupt (IERxI) is issued to the
7. When the last data is received, a receive normal completion (RxF) interrupt (IERSI) occurs. In
Notes: 1. As a receive status interrupt (IERSI), the receive error termination (RxE) interrupt as
completed before the header reception. Accordingly, the RSS flag is stipulated that it changes
at the timing of starting reception.
(receive status interrupt (IERSI)) will occur and the SRE flag is set to 1. In this case, the DTC
initialization described in (2) is performed. After initialization, the RxS flag is cleared to 0.
occurs, and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the
RxRDY flag.
bytes after loading the receive data to the RAM. In this case, the DTC does not clear the
RxRDY flag. It, however, clears the DTC enable register G (DTCEG). Accordingly, hereafter,
no transfer request will be issued to the DTC.
CPU. In this interrupt handling routine, the RxRDY flag is cleared.
this case, the CPU clears the RxF flag in order to complete the normal completion interrupt.
The SRE flag is cleared to 0.
2. The interrupt occurs after the DTC transfer has been completed. Accordingly, the
well as the receive start detection (RxS) and receive normal completion (RxF)
interrupts must be enabled. If an error termination interrupt is disabled, no interrupt is
generated even if the reception is terminated by an error.
interrupt described in item 6 actually occurs after item 7 above.
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 593 of 928
REJ09B0099-0600