DF2506BR26DV Renesas Electronics America, DF2506BR26DV Datasheet - Page 651

• Manufacturer Part Number: DF2506BR26DV
• Description: IC H8S/2506 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2506BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6
17.6.1
The IEB is enabled or disabled by setting the module stop control register. In the initial state, the
IEB is disabled. After the module stop mode is canceled, registers can be accessed. For details, see
section 22, Power-Down Modes.
17.6.2
1. The TxRDY flag indicates that IETBR is empty. Writing to IETBR by the DTC clears the
2. If the CPU fails to write to IETBR by the timing of the frame transmission or if the number of
3. The IEB decides that an underrun error occurred when the data is loaded from IETBR to the
4. On the receive side, the unit decides that a timing error has occurred because the
5. In data transfer using the DTC, the TxRDY flag in IETSR is not cleared after the last byte data
6. Although the DTC is used as described in item 5, if the number of DTC transfer words is less
TxRDY flag. Meanwhile, the TxRDY flag must be cleared by software since writing to IETBR
by the CPU does not clear the TxRDY flag.
transfer words is less than the length specified by the message length bits, an underrun error
occurs.
transmit shift register while the TxRDY flag is set to 1. In this case, the IEB sets the TxE flag
in IETSR and enters the wait state. The UE flag in IETEF is also set to 1.
communications are terminated.
is transferred to IETBR and a CPU interrupt caused by the DTC interrupt will occur.
If the TxRDY flag is not cleared in this CPU interrupt handling routine, an underrun error will
occur when the last byte data is loaded from IETBR to the transmit shift register. In this case,
if the LUEE bit is cleared to 0 (initial value), no underrun error occurs and the last byte of the
data field is transmitted correctly. (if the LUEE bit is set to 1, an underrun error occurs.)
than the length specified by the message length bits, the LUEE bit setting is invalid. (The
LUEE bit is valid only when data is transmitted for the number of bytes specified by the
message length bits has been transmitted.) In this case, an underrun error occurs, data is
transmitted for one byte less than the DTC transfer words, and the transfer is terminated by a
transmit error.
Usage Notes
Setting Module Stop Mode
TxRDY Flag and Underrun Error
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 603 of 928
REJ09B0099-0600