LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 791
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
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- Download datasheet (5Mb)
NXP Semiconductors
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.3
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
Chapter 33: LPC24XX EmbeddedICE
1
2
3
4
Chapter 34: LPC24XX Embedded Trace Module (ETM)
1
2
3
3.1
4
UM10237_4
User manual
Programming the GPDMA. . . . . . . . . . . . . . . 718
Register description . . . . . . . . . . . . . . . . . . . 720
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 741
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 745
Endian behavior . . . . . . . . . . . . . . . . . . . . . . 714
Error conditions . . . . . . . . . . . . . . . . . . . . . . 716
Channel hardware . . . . . . . . . . . . . . . . . . . . 717
DMA request priority . . . . . . . . . . . . . . . . . . . 717
Interrupt generation . . . . . . . . . . . . . . . . . . . 717
The completion of the DMA transfer
indication . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
DMA system connections . . . . . . . . . . . . . . . 717
Enabling the GPDMA . . . . . . . . . . . . . . . . . . 718
Disabling the GPDMA. . . . . . . . . . . . . . . . . . 718
Enabling a DMA channel . . . . . . . . . . . . . . . 719
Disabling a DMA channel . . . . . . . . . . . . . . . 719
Disabling a DMA channel without losing data in
the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Setup a new DMA transfer . . . . . . . . . . . . . . 719
Disabling a DMA channel and losing data in the
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Halting a DMA transfer . . . . . . . . . . . . . . . . . 719
Programming a DMA channel. . . . . . . . . . . . 720
General GPDMA registers . . . . . . . . . . . . . . 721
Interrupt Status Register (DMACIntStatus -
0xFFE0 4000) . . . . . . . . . . . . . . . . . . . . . . . . 721
Interrupt Terminal Count Status Register
(DMACIntTCStatus - 0xFFE0 4004) . . . . . . . 722
Interrupt Terminal Count Clear Register
(DMACIntClear - 0xFFE0 4008) . . . . . . . . . . 722
Interrupt Error Status Register
(DMACIntErrorStatus - 0xFFE0 400C) . . . . . 722
Interrupt Error Clear Register (DMACIntErrClr -
0xFFE0 4010) . . . . . . . . . . . . . . . . . . . . . . . . 723
Raw Interrupt Terminal Count Status Register
(DMACRawIntTCStatus - 0xFFE0 4014) . . . 723
Raw Error Interrupt Status Register
(DMACRawIntErrorStatus - 0xFFE0 4018). . 723
Enabled Channel Register (DMACEnbldChns -
0xFFE0 401C) . . . . . . . . . . . . . . . . . . . . . . . 724
Software Burst Request Register
(DMACSoftBReq - 0xFFE0 4020). . . . . . . . . 724
Software Single Request Register
(DMACSoftSReq - 0xFFE0 4024). . . . . . . . . 725
ETM configuration . . . . . . . . . . . . . . . . . . . . 744
Rev. 04 — 26 August 2009
6.1.11
6.1.12
6.1.13
6.1.14
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
7
8
8.1
8.2
8.3
9
9.1
9.2
10
10.1
10.2
10.3
11
5
6
7
5
6
7
Chapter 36: LPC24XX Supplementary information
Address generation . . . . . . . . . . . . . . . . . . . 733
Scatter/Gather . . . . . . . . . . . . . . . . . . . . . . . . 733
Interrupt requests . . . . . . . . . . . . . . . . . . . . . 735
GPDMA data flow . . . . . . . . . . . . . . . . . . . . . 736
Flow control. . . . . . . . . . . . . . . . . . . . . . . . . . 739
JTAG function select. . . . . . . . . . . . . . . . . . . 742
Register description . . . . . . . . . . . . . . . . . . . 742
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 742
Register description . . . . . . . . . . . . . . . . . . . 745
Reset state of multiplexed pins . . . . . . . . . . 746
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 747
Software Last Burst Request Register
(DMACSoftLBreq - 0xFFE0 4028) . . . . . . . . 725
Software Last Single Request Register
(DMACSoftLSReq - 0xFFE0 402C) . . . . . . . 725
Configuration Register (DMACConfiguration -
0xFFE0 4030) . . . . . . . . . . . . . . . . . . . . . . . 726
Synchronization Register (DMACSync -
0xFFE0 4034) . . . . . . . . . . . . . . . . . . . . . . . 726
Channel registers. . . . . . . . . . . . . . . . . . . . . 727
Channel Source Address Registers
(DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120). . . . . . . . 727
Channel Destination Address Registers
(DMACC0DestAddr - 0xFFE0 4104 and
DMACC1DestAddr - 0xFFE0 4124). . . . . . . 727
Channel Linked List Item Registers (DMACC0LLI
- 0xFFE0 4108 and DMACC1LLI -
0xFFE0 4128) . . . . . . . . . . . . . . . . . . . . . . . 728
Channel Control Registers (DMACC0Control -
0xFFE0 410C and DMACC0Control -
0xFFE0 412C) . . . . . . . . . . . . . . . . . . . . . . . 728
Protection and Access Information . . . . . . . 730
Channel Configuration Registers
(DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130) . . . 731
Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 732
Flow control and transfer type . . . . . . . . . . . 733
Linked List Items . . . . . . . . . . . . . . . . . . . . . 733
Programming the GPDMA for scatter/gather DMA
734
Example of scatter/gather DMA . . . . . . . . . . 734
Hardware interrupt sequence flow . . . . . . . . 736
Interrupt polling sequence flow . . . . . . . . . . 736
Peripheral-to-memory, or Memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Peripheral-to-peripheral DMA flow. . . . . . . . 737
Memory-to-memory DMA flow . . . . . . . . . . . 738
UM10237
© NXP B.V. 2009. All rights reserved.
791 of 792
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