LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 783
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
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NXP Semiconductors
5
6
6.1
6.2
6.3
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Chapter 16: LPC24XX UART0/2/3
1
2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
UM10237_4
User manual
Modes of operation . . . . . . . . . . . . . . . . . . . . 395
Pin configuration . . . . . . . . . . . . . . . . . . . . . . 395
Register description . . . . . . . . . . . . . . . . . . . 400
Basic configuration . . . . . . . . . . . . . . . . . . . . 423
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 423
Register description . . . . . . . . . . . . . . . . . . . 424
Connecting port U1 to an external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Connecting USB as a two-port host . . . . . . . 399
Connecting USB as one port host and one port
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
USB Interrupt Status Register (USBIntSt -
0xE01F C1C0) . . . . . . . . . . . . . . . . . . . . . . . 401
OTG Interrupt Status Register (OTGIntSt -
0xE01F C100) . . . . . . . . . . . . . . . . . . . . . . . 402
OTG Interrupt Enable Register (OTGIntEn -
0xFFE0 C104) . . . . . . . . . . . . . . . . . . . . . . . 402
OTG Interrupt Set Register (OTGIntSet -
0xFFE0 C20C) . . . . . . . . . . . . . . . . . . . . . . . 402
OTG Interrupt Clear Register (OTGIntClr -
0xFFE0 C10C) . . . . . . . . . . . . . . . . . . . . . . . 402
OTG Status and Control Register (OTGStCtrl -
0xFFE0 C110). . . . . . . . . . . . . . . . . . . . . . . . 402
OTG Timer Register (OTGTmr -
0xFFE0 C114). . . . . . . . . . . . . . . . . . . . . . . . 404
OTG Clock Control Register (OTGClkCtrl -
0xFFE0 CFF4) . . . . . . . . . . . . . . . . . . . . . . . 404
OTG Clock Status Register (OTGClkSt -
0xFFE0 CFF8) . . . . . . . . . . . . . . . . . . . . . . . 405
I2C Receive Register (I2C_RX -
0xFFE0 C300) . . . . . . . . . . . . . . . . . . . . . . . 406
UARTn Receiver Buffer Register (U0RBR -
0xE000 C000, U2RBR - 0xE007 8000, U3RBR -
0xE007 C000 when DLAB = 0, Read Only) . 427
UARTn Transmit Holding Register (U0THR -
0xE000 C000, U2THR - 0xE007 8000, U3THR -
0xE007 C000 when DLAB = 0, Write Only) . 427
UARTn Divisor Latch LSB Register (U0DLL -
0xE000 C000, U2DLL - 0xE007 8000, U3DLL -
0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM -
0xE000 C004, U2DLL - 0xE007 8004, U3DLL -
0xE007 C004 when DLAB = 1). . . . . . . . . . . 427
UARTn Interrupt Enable Register (U0IER -
0xE000 C004, U2IER - 0xE007 8004, U3IER -
0xE007 C004 when DLAB = 0). . . . . . . . . . . 428
UARTn Interrupt Identification Register (U0IIR -
0xE000 C008, U2IIR - 0xE007 8008, U3IIR -
0x7008 C008, Read Only) . . . . . . . . . . . . . . 429
UARTn FIFO Control Register (U0FCR -
0xE000 C008, U2FCR - 0xE007 8008, U3FCR -
0xE007 C008, Write Only) . . . . . . . . . . . . . . 431
Rev. 04 — 26 August 2009
7.11
7.12
7.13
7.14
7.15
7.16
8
8.1
8.2
9
9.1
9.1.1
9.2
10
4.7
4.8
4.9
4.10
4.10.1
4.10.2
4.11
4.12
4.12.1
4.12.1.1
4.12.1.2
4.13
Chapter 36: LPC24XX Supplementary information
HNP support . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Clocking and power management. . . . . . . . 419
USB OTG controller initialization . . . . . . . . 421
I2C Transmit Register (I2C_TX -
0xFFE0 C300) . . . . . . . . . . . . . . . . . . . . . . . 406
I2C Status Register (I2C_STS -
0xFFE0 C304) . . . . . . . . . . . . . . . . . . . . . . . 406
I2C Control Register (I2C_CTL -
0xFFE0 C308) . . . . . . . . . . . . . . . . . . . . . . . 408
I2C Clock High Register (I2C_CLKHI -
0xFFE0 C30C) . . . . . . . . . . . . . . . . . . . . . . . 409
I2C Clock Low Register (I2C_CLKLO -
0xFFE0 C310) . . . . . . . . . . . . . . . . . . . . . . . 410
Interrupt handling . . . . . . . . . . . . . . . . . . . . . 410
B-device: peripheral to host switching . . . . . 412
Remove D+ pull-up . . . . . . . . . . . . . . . . . . . . 414
Add D+ pull-up . . . . . . . . . . . . . . . . . . . . . . . . 415
A-device: host to peripheral HNP switching. 415
Set BDIS_ACON_EN in external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Clear BDIS_ACON_EN in external OTG trans-
ceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Discharge V
Load and enable OTG timer . . . . . . . . . . . . . 419
Stop OTG timer . . . . . . . . . . . . . . . . . . . . . . . 419
Suspend host on port 1 . . . . . . . . . . . . . . . . . 419
Device clock request signals . . . . . . . . . . . . 420
Host clock request signals . . . . . . . . . . . . . . 421
Power-down mode support . . . . . . . . . . . . . 421
UARTn Line Control Register (U0LCR -
0xE000 C00C, U2LCR - 0xE007 800C, U3LCR -
0xE007 C00C) . . . . . . . . . . . . . . . . . . . . . . . 431
UARTn Line Status Register (U0LSR -
0xE000 C014, U2LSR - 0xE007 8014, U3LSR -
0xE007 C014, Read Only) . . . . . . . . . . . . . . 432
UARTn Scratch Pad Register (U0SCR -
0xE000 C01C, U2SCR - 0xE007 801C U3SCR -
0xE007 C01C) . . . . . . . . . . . . . . . . . . . . . . . 434
UARTn Auto-baud Control Register (U0ACR -
0xE000 C020, U2ACR - 0xE007 8020, U3ACR -
0xE007 C020) . . . . . . . . . . . . . . . . . . . . . . . 434
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 435
IrDA Control Register for UART3 Only (U3ICR -
0xE007 C024) . . . . . . . . . . . . . . . . . . . . . . . 437
UARTn Fractional Divider Register (U0FDR -
0xE000 C028, U2FDR - 0xE007 8028, U3FDR -
0xE007 C028) . . . . . . . . . . . . . . . . . . . . . . . 437
Baudrate calculation . . . . . . . . . . . . . . . . . . 438
Example 1: PCLK = 14.7456 MHz,
BR = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Example 2: PCLK = 12 MHz, BR = 115200 . 440
UARTn Transmit Enable Register (U0TER -
0xE000 C030, U2TER - 0xE007 8030, U3TER -
0xE007 C030) . . . . . . . . . . . . . . . . . . . . . . . 440
BUS
. . . . . . . . . . . . . . . . . . . . . . . 418
UM10237
© NXP B.V. 2009. All rights reserved.
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