LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 736

• Manufacturer Part Number: LPC2478FBD208,551
• Description: IC ARM7 MCU 512K LCD 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2478FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
• Development Tools By Supplier: OM11015, OM11019, OM11022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4363; 935284069551; LPC2478FBD208-S

NXP Semiconductors
10. GPDMA data flow
UM10237_4
User manual
9.1 Hardware interrupt sequence flow
9.2 Interrupt polling sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
Used when the GPDMA interrupt request signal is either masked out, disabled in the
interrupt controller or disabled in the processor. When polling the GPDMA, you must:
This section describes the GPDMA data flow sequences for the four allowed transfer
types:
Each transfer type can have either the peripheral or the GPDMA as the flow controller so
there are eight possible control scenarios.
Table 32–676
1. Read the DMACIntStatus Register to determine which channel generated the
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
3. Read the DMACIntErrorStatus Register to determine whether the interrupt was
4. Service the interrupt request.
5. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
1. Read the DMACIntStatus Register. If none of the bits are HIGH repeat this step,
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
3. Service the interrupt request.
4. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
•
•
•
•
interrupt. If more than one request is active it is recommended that the highest priority
channels be checked first.
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
generated due to an error occurring. A HIGH bit indicates that an error occurred.
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
otherwise go to step 2. If more than one request is active it is recommended that the
highest priority channels be checked first.
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
Memory-to-peripheral.
Peripheral-to-memory.
Memory-to-memory.
Peripheral-to-peripheral.
indicates the request signals used for each type of transfer.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
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