LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 732
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 732 of 792
- Download datasheet (5Mb)
NXP Semiconductors
Table 674. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
UM10237_4
User manual
Bit
4:1
5
9:6
10
13:11 FlowCntrl
14
15
16
17
18
31:19 -
Symbol
SrcPeripheral
-
DestPeriphera
l
-
IE
ITC
L
A
H
DMACC1Configuration - address 0xFFE0 4130) bit description
6.2.7 Lock control
Value Description
0000
0001
0010
0011
0100
0101
0110
0111
or
1xxx
-
-
0
1
0
1
Set the lock bit by programming bit 16 in the DMACCxConfiguration Register.
When a burst occurs, the AHB arbiter must not de-grant the master during the burst until
the lock is deasserted. The GPDMA can be locked for a a single burst such as a long
source fetch burst or a long destination drain burst. The GPDMA does not usually assert
the lock continuously for a source fetch burst followed by a destination drain burst.
is ignored if the source of the transfer is from memory.
SSP0 Tx
SSP0 Rx
SSP1 Tx
SSP1 Rx
SD/MMC
I2S channel 0
I2S channel 1
These values are reserved and should not be used.
Reserved, do not modify, masked on read.
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory. See the
SrcPeripheral symbol description for values.
Reserved, do not modify, masked on read.
Flow control and transfer type. This value indicates the flow controller and transfer
type. The flow controller can be the GPDMA, the source peripheral, or the
destination peripheral.The transfer type can be memory-to-memory,
memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.
relevant channel.
Terminal count interrupt mask. When cleared this bit masks out the terminal count
interrupt of the relevant channel.
Lock. When set, this bit enables locked transfers.
Active. This value can be used with the Halt and Channel Enable bits to cleanly
disable a DMA channel. Writing to this bit has no effect.
There is no data in the FIFO of the channel.
The channel FIFO has data.
Halt. The contents of the channel FIFO are drained. This value can be used with the
Active and Channel Enable bits to cleanly disable a DMA channel.
Enable DMA requests.
Ignore further source DMA requests.
Reserved, do not modify, masked on read.
Source peripheral. This value selects the DMA source request peripheral.This field
Interrupt error mask. When cleared this bit masks out the error interrupt of the
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
732 of 792
Reset
Value
0
NA
0
NA
0
0
0
0
0
NA
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