LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 662

• Manufacturer Part Number: LPC2478FBD208,551
• Description: IC ARM7 MCU 512K LCD 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2478FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
• Development Tools By Supplier: OM11015, OM11019, OM11022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4363; 935284069551; LPC2478FBD208-S

1. Features
2. Applications
3. Description
UM10237_4
User manual
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32 bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
and the maximum Watchdog interval is (T
The Watchdog should be used in the following manner:
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UM10237
Chapter 27: LPC24XX WatchDog Timer (WDT)
Rev. 04 — 26 August 2009
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32 bit timer with internal pre-scaler.
Selectable time period from (T
T
The Watchdog clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock (PCLK, see
gives a wide range of potential timing choices for Watchdog operation under different
power reduction conditions. It also provides the ability to run the Watchdog timer from
an entirely internal source that is not dependent on an external crystal and its
associated components and wiring, for increased reliability.
Set the Watchdog timer constant reload value in WDTC register.
Setup mode in WDMOD register.
Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
Watchdog should be fed again before the Watchdog counter underflows to prevent
reset/interrupt.
WDCLK
× 4.
Rev. 04 — 26 August 2009
Section 3–3.2 “Reset” on page 31
WDCLK
× 256 × 4) to (T
WDCLK
× 2
32
× 4) in multiples of (T
WDCLK
× 2
32
of this document.
× 4) in multiples of
© NXP B.V. 2009. All rights reserved.
Table
WDCLK
User manual
WDCLK
4–56). This
× 256 × 4)
662 of 792
× 4).