LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 640
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 640 of 792
- Download datasheet (5Mb)
NXP Semiconductors
Table 559: PWM Timer Control Register (PWM0TCR - address 0xE001 4004 PWM1TCR address 0xE001 8004) bit
UM10237_4
User manual
Bit
0
1
2
3
4
7:5
Symbol
Counter Enable 1
Counter Reset
-
PWM Enable
Master Disable
(PWM0 only)
-
description
6.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and
Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address
PWM1TCR 0xE001 8004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in
Bit
9
10
15:11 -
Value
0
1
0
1
0
1
0
Symbol
PWMMR5 Interrupt Interrupt flag for PWM match channel 5.
PWMMR6 Interrupt Interrupt flag for PWM match channel 6.
0xE001 8000) bit description
Description
The PWM Timer Counter and PWM Prescale Counter are
enabled for counting.
The counters are disabled.
The PWM Timer Counter and the PWM Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until this bit is returned to zero.
Clear reset.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
PWM mode is enabled (counter resets to 1). PWM mode
causes the shadow registers to operate in connection with
the Match registers. A program write to a Match register will
not have an effect on the Match result until the
corresponding bit in PWMLER has been set, followed by the
occurrence of a PWM Match 0 event. Note that the PWM
Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being
enabled. Otherwise a Match event will not occur to cause
shadow register contents to become effective.
Timer mode is enabled (counter resets to 0).
The two PWMs may be synchronized using the Master
Disable control bit. The Master disable bit of the Master
PWM (PWM0 module) controls a secondary enable input to
both PWMs, as shown in
This bit has no function in the Slave PWM (PWM1).
PWM0 is the master, and both PWMs are enabled for
counting.
The PWM’s are used independently, and the individual
Counter Enable bits are used to control the PWM’s.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Figure
25–132.
Table
25–559.
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
NA
0
0
NA
640 of 792
Reset
Value
0
0
NA
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