LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 63
![IC ARM7 MCU 512K LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 63 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
3.4.8 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
Table 60.
Encoding of reduced power modes
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power-down modes.
three reduced power modes supported by the LPC2400.
Table 61.
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power-down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power-down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power-down without waking the
Bit
4
6:3
7
PM2, PM1, PM0 Description
000
001
101
010
110
Others
-
Symbol
BORD
PM2
Power Mode Control register (PCON - address 0xE01F C0C0) bit description
Encoding of reduced power modes
Power-down mode. Causes the oscillator and all on-chip clocks to be stopped.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
Section 4–3.4.3
Deep power-down mode. This is the most extreme power saving mode. As in
Reserved, not currently used.
Description
Brown-Out Reset Disable. When BORD is 1, the second stage of low
voltage detection (2.6 V) will not cause a chip reset.
When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Power mode control bit 2. See
Normal operation
Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See
details.
Sleep mode. This mode is similar to Power-down mode (the oscillator and all
on-chip clocks are stopped), but the flash memory is left in Standby mode. This
allows a more rapid wakeup than Power-down mode because the flash
reference voltage regulator start-up time is not needed. See
details.
Power-down mode, Deep power-down mode causes the oscillator and all
on-chip clocks to be stopped, but also turns off the on-chip DC-DC converter
that supplies power to internal circuitry. See
Section 3–4
Rev. 04 — 26 August 2009
for details.
for details of Brown-Out detection.
Chapter 4: LPC24XX Clocking and power control
Table 4–61
Table 4–61
below shows the encoding for the
for details.
Section 4–3.4.4
Section 4–3.4.1
UM10237
© NXP B.V. 2009. All rights reserved.
Section 4–3.4.2
for details.
63 of 792
Reset
value
0
NA
0
for
for
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