LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 527

• Manufacturer Part Number: LPC2478FBD208,551
• Description: IC ARM7 MCU 512K LCD 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2478FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
• Development Tools By Supplier: OM11015, OM11019, OM11022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4363; 935284069551; LPC2478FBD208-S

NXP Semiconductors
UM10237_4
User manual
Fig 94. SPI data transfer format (CPHA = 0 and CPHA = 1)
Cycle # CPHA = 0
Cycle # CPHA = 1
MOSI (CPHA = 0)
MISO (CPHA = 0)
MOSI (CPHA = 1)
MISO (CPHA = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
CPHA = 0
CPHA = 1
SSEL
The data and clock phase relationships are summarized in
summarizes the following for each setting of CPOL and CPHA.
Table 459. SPI Data To Clock Phase Relationship
The definition of when an 8 bit transfer starts and stops is dependent on whether a device
is a master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
CPOL and CPHA settings First data driven
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
•
•
•
When the first data bit is driven.
When all other data bits are driven.
When data is sampled.
BIT 1
BIT 1
1
BIT 1
BIT 1
1
BIT 2
BIT 2
2
BIT 2
BIT 2
Rev. 04 — 26 August 2009
2
BIT 3
BIT 3
3
Prior to first SCK rising edge SCK falling edge
First SCK rising edge
Prior to first SCK falling edge SCK rising edge
First SCK falling edge
BIT 3
BIT 3
3
BIT 4
BIT 4
4
BIT 4
BIT 4
4
BIT 5
BIT 5
5
BIT 5
BIT 5
5
BIT 6
BIT 6
6
BIT 6
BIT 6
6
Other data driven Data sampled
SCK rising edge
SCK falling edge
BIT 7
BIT 7
7
BIT 7
BIT 7
Table
7
Chapter 19: LPC24XX SPI
BIT 8
BIT 8
8
19–459. This table
BIT 8
BIT 8
8
UM10237
© NXP B.V. 2009. All rights reserved.
SCK rising edge
SCK falling edge
SCK falling edge
SCK rising edge
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