AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 887
AT91SAM9R64-CU
Manufacturer Part Number
AT91SAM9R64-CU
Description
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9R64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
49
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
144LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9R64-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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47.2.7
47.2.7.1
47.2.8
47.2.8.1
47.2.9
47.2.9.1
6289C–ATARM–28-May-09
Serial Peripheral Interface (SPI)
Shutdown Controller
Static Memory Controller (SMC)
SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
SHDN Signal may be Driven to Low Level Voltage During Device Power-on
SMC: Chip Select Parameters Modification
then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of
MCK/(2 x DIV).
None.
If the SPI is used in the following configuration:
then an additional pulse will be generated on output PSCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be
driven to low level voltage after a delay. This delay is linked to the startup time of the slow clock
selected by OSCSEL signal.
If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE estab-
lishment does not occur and the system does not start.
1. VDDCORE must be established within the delay corresponding to the startup time of the slow
clock selected by OSCSEL.
2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output
(EN_REG) can be connected to a PIO and used to enter the shutdown mode.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
• master mode
• CPOL=1 and NCPHA =0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9R64/RL64 Preliminary
887
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