AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 426

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

33.10 Two-wire Interface (TWI) User Interface
Table 33-5.
426
Offset
0x00
0x04
0x08
0x0C
0x10
0x20
0x24
0x28
0x2C
0x30
0x34
0x38 - 0xFC
0x100 - 0x124
AT91SAM9R64/RL64 Preliminary
Two-wire Interface (TWI) User Interface
Register
Control Register
Master Mode Register
Slave Mode Register
Internal Address Register
Clock Waveform Generator Register
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Receive Holding Register
Transmit Holding Register
Reserved
Reserved for the PDC
TWI_CWGR
TWI_MMR
TWI_IADR
TWI_SMR
TWI_RHR
TWI_THR
TWI_IMR
TWI_IDR
TWI_IER
TWI_CR
TWI_SR
Name
–
–
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Access
–
–
6289C–ATARM–28-May-09
0x00000000
0x00000000
0x00000000
0x00000000
0x0000F009
0x00000000
0x00000000
0x00000000
Reset State
N / A
N / A
N / A
–
–