AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 585

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6289C–ATARM–28-May-09
Note:
Note:
4. Write the channel configuration information into the DMAC_CFGx register for channel
5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
7. Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
16. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx
17. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets
x.
the last) are set as shown in Row 6 of
LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in
Row 1 of
list items.
the last) are non-zero and point to the next Linked List Item.
the start destination buffer address proceeding that LLI fetch.
locations of all LLIs in memory is cleared.
DMAC_SPIPx register for channel x.
the DMAC_DPIPx register for channel x.
ing to the DMAC_EBCISR register.
Table 37-1 on page
Linked List item.
is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN
register is enabled.
register is written out to the same location on the same layer
(DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
transfer. Only DMAC_CTRLAx register is written out, because only the
DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by
hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate
buffer completion Therefore, software can poll the LLI.DMAC_CTRLAx.DONE field of
the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has
completed.
the buffer complete interrupt. The DMAC samples the row number as shown in
37-1 on page
Hardware sets the transfer complete interrupt and disables the channel. You can either
respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll
for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is
not used.
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit
is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was
cleared at the start of the transfer.
Table
575. If the DMAC is in Row 1, then the DMAC transfer has completed.
37-1.
575.
Figure 37-4 on page 574
AT91SAM9R64/RL64 Preliminary
Table 37-1 on page 575
shows a Linked List example with two
while the
Table
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