AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 154

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.7
21.7.1
21.7.1.1
21.7.1.2
6289C–ATARM–28-May-09
Implementation Examples
16-bit SDRAM
Hardware Configuration
Software Configuration
(Not used A12)
The following hardware configurations are given for illustration only. The user should refer to the
memory manufacturer web site to check current device availability.
The following configuration has to be performed:
The Data Bus Width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in
“SDRAM Controller (SDRAMC)”.
A[0..14]
D[0..15]
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
Select Assignment Register located in the bus matrix memory space.
CFIOR_NBS1_NWR1
SDCS_NCS1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
A0
SDA10
SDCKE
SDCK
SDWE
BA0
BA1
CAS
RAS
AT91SAM9R64/RL64 Preliminary
1%6
1%6
SDA10
BA0
BA1
SDCKE
SDCK
CAS
RAS
SDWE
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
U1
U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
A12
N.C
CKE
CLK
DQML
DQMH
CAS
RAS
WE
CS
TSOP54 PACKAGE
MT48LC16M16A2
MT48LC16M16A2
256 Mbits
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VDD
VDD
VSS
VSS
VSS
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
C1 1
C1 1
C2 1
C2 1
C3 1
C3 1
C4 1
C4 1
C5 1
C5 1
C6 1
C6 1
C7 1
C7 1
154