AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 660

MCU ARM9 64K SRAM 144-LFBGA

AT91SAM9R64-CU

Manufacturer Part Number
AT91SAM9R64-CU
Description
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9R64-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
49
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
144LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Table 39-10. Dithering Algorithm for Color Mode
Note:
39.5.2.7
660
Frame
N+1
N+1
N+1
N+1
N+1
N+1
N+2
N+2
N+2
N+2
N+2
N+2
N
N
N
N
N
N
Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF.
gi = green pixel component OFF. bi = blue pixel component OFF.
AT91SAM9R64/RL64 Preliminary
green_data_0
green_data_1
green_data_0
green_data_1
green_data_0
green_data_1
blue_data_0
blue_data_1
blue_data_0
blue_data_1
blue_data_0
blue_data_1
Shifter
red_data_0
red_data_1
red_data_0
red_data_1
red_data_0
red_data_1
Signal
both pixels, with the dithering pattern to apply to all of them being DP2_3 = “1101 1011 0110”.
Table 39-10
Dual Scan Configuration, each panel data bus acts like in the equivalent single scan
configuration.)
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome
mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the
data according to the output interface. This interface can be programmed in the DISTYPE,
SCANMOD, and IFWIDTH fields of the LDCCON3 register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCAN-
MODE field selects between single and dual scan modes; in TFT mode, only single scan is
supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single
scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see
page
Shadow Level
677.
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
shows the output sequence in the data output bus for single scan configurations. (In
Bit used
3
2
1
0
3
2
3
2
1
0
3
2
3
2
1
0
3
2
Dithering Pattern
1011
1011
0110
0110
1101
1101
1101
1101
1101
1101
1011
1011
1011
1011
0110
0110
0110
0110
“LCD Controller (LCDC) User Interface” on
4-bit LCDD
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
8-bit LCDD
LCDD[6]
LCDD[3]
LCDD[7]
LCDD[6]
LCDD[4]
LCDD[3]
LCDD[7]
LCDD[6]
LCDD[4]
LCDD[3]
LCDD[7]
LCDD[5]
LCDD[4]
LCDD[2]
LCDD[5]
LCDD[2]
LCDD[5]
LCDD[2]
6289C–ATARM–28-May-09
Output
R0
G0
R1
G1
B1
R0
B0
R1
G1
G0
B0
B1
b0
g0
b1
g1
r0
r1

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