AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 500

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 35-3. SSC Functional Block Diagram
35.6.1
500
AT91SAM9R64/RL64 Preliminary
Clock Management
APB
MCK
PDC
Interface
Divider
Clock
User
The transmitter clock can be generated by:
The receiver clock can be generated by:
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider
• an external clock received on the RK I/O pad
• the transmitter clock
• the internal clock divider
Interrupt Control
AIC
TF
RF
TX Clock
RF
TF
TK Input
RK Input
RX clock
Selector
Selector
Start
Start
TX PDC
RX PDC
Load Shift
Load Shift
Transmitter
Transmit Clock
Receive Clock
Controller
Controller
Receiver
Transmit Holding
Receive Holding
Register
Register
Transmit Shift Register
Receive Shift Register
RX Clock
TX clock
Holding Register
Holding Register
Transmit Sync
Receive Sync
Clock Output
Clock Output
Frame Sync
Frame Sync
Controller
Controller
Controller
Controller
6289C–ATARM–28-May-09
TK
RD
TD
RK
RF
TF