AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 143

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.4
21.4.1
Table 21-3.
Notes:
6289C–ATARM–28-May-09
Signals:
EBI_
Controller
D0 - D7
D8 - D15
D16 - D23
D24 - D31
A0/NBS0
A1/NWR2/NBS2
A2 - A22
A23 - A25
NCS0
NCS1/SDCS
NCS2
NCS3/NANDCS
NCS4/CFCS0
NCS5/CFCS1
NRD/CFOE
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
Application Example
1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. BEx: Byte x Enable (x = 0,1,2 or 3)
Hardware Interface
EBI Pins and External Static Devices Connections
8-bit Static
A[23:25]
D0 - D7
Device
A[2:22]
Table 21-3 on page 143
external devices for each Memory Controller.
WE
CS
CS
CS
CS
CS
CS
OE
A0
A1
–
–
–
–
–
2 x 8-bit
Devices
D8 - D15
A[22:24]
D0 - D7
A[1:21]
Static
WE
WE
CS
CS
CS
CS
CS
CS
OE
A0
–
–
–
–
(1)
(1)
details the connections to be applied between the EBI pins and the
16-bit Static
Pins of the Interfaced Device
D8 - D15
A[22:24]
D0 - D7
Device
A[1:21]
AT91SAM9R64/RL64 Preliminary
NUB
NLB
WE
CS
CS
CS
CS
CS
CS
OE
A0
–
–
–
SMC
D16 - D23
D24 - D31
4 x 8-bit
Devices
D8 - D15
A[21:23]
D0 - D7
A[0:20]
Static
WE
WE
WE
WE
CS
CS
CS
CS
CS
CS
OE
–
(2)
(2)
(2)
(2)
2 x 16-bit
D16 - D23
D24 - D31
Devices
A[21:23]
D0 - D7
D8 - 15
A[0:20]
NUB
NUB
Static
NLB
NLB
WE
CS
CS
CS
CS
CS
CS
OE
(3)
(4)
(3)
(4)
32-bit Static
D16 - D23
D24 - D31
A[21:23]
D0 - D7
Device
D8 - 15
A[0:20]
BE0
BE2
BE1
BE3
WE
CS
CS
CS
CS
CS
CS
OE
(5)
(5)
(5)
(5)
143