AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 791

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

37.8.3
37.9
32015G–AVR32–09/09
SAB address map
Boundary-Scan Chain
This register is intended to be used when programming the device, to avoid running partially
downloaded code. The following procedure is recommended:
• RESET = OCD | APP | DCACHE | ICACHE | CPU
• RESET = ICACHE | CPU
• Perform the programming operations
• RESET = 0
It is not recommended to use the RESET register for other purposes than described above, as
operations may not function correctly when parts of the system are reset.
The Boundary-Scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atmel web site.
The Service Access Bus (SAB) gives the user access to the internal address space and other
features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32
LSBs are decoded within the slave’s address space. The SAB slaves are shown in
Table 37-12. SAB Slaves, addresses and descriptions.
DCACHE
APP
OCD
HSB uncached
– This will bring the entire system back to its reset state, regardless of the preceding
– This keeps the ICache and CPU from fetching and executing partially downloaded
– The CPU will start executing from the reset vector.
HSB cached
Unallocated
Reserved
state.
instructions.
Slave
OCD
Data cache and JTAG SAB interface
HSB and PB buses
On-Chip Debug logic and registers
Address [35:32]
Other
0x0
0x1
0x4
0x5
Description
Intentionally unallocated
OCD registers
HSB memory space, as seen by the CPU through the data
cache
Alternative mapping for HSB space, as seen by the CPU
bypassingthe data cache.
Unused
AT32AP7001
Table
37-12.
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