AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 613

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32.6.6.6
32015G–AVR32–09/09
Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism
does not operate.
A Zero Length Packet can be sent by setting just the TX_PKTRDY flag in the EPTSETSTAx
register.
The USBA integrates a DMA host controller. This DMA controller can be used to transfer a buf-
fer from the memory to the DPR or from the DPR to the processor memory under the USBA
control. The DMA can be used for all transfer types except control transfer.
Example DMA configuration:
1. Program DMAADDRESSx with the address of the buffer that should be transfer.
2. Enable the interrupt of the DMA in IEN
3. Program DMACONTROLx:
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention
of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is
done by hardware.
A transfer descriptor can be used. Instead of programming the register directly, a descriptor
should be programmed and the address of this descriptor is then given to DMANXTDSC to be
processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in DMACONTROLx
register.
The structure that defines this transfer descriptor must be aligned.
Each buffer to be transferred must be described by a DMA Transfer descriptor (see
Channel Transfer Descriptor” on page
transfer of the buffer, the USBA may fetch a new transfer descriptor from the memory address
pointed by the DMANXTDSCx register. Once the transfer is complete, the transfer status is
updated in the DMASTATUSx register.
To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be
stopped. To do so, INTDIS_DMA and TX_BK_RDY may be set in the EPTCTLENBx register. It
is also possible for the application to wait for the completion of all transfers. In this case the
LDNXT_DSC field in the last transfer descriptor DMACONTROLx register must be set to 0 and
CHANN_ENB set to 1.
Then the application can chain a new transfer descriptor.
The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is trig-
gered. This can be used to stop DMA transfers in case of errors.
The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the DMA-
CONTROLx register).
– Size of buffer to send: size of the buffer to be sent to the host.
– END_B_EN: The endpoint can validate the packet (according to the values
– END_BUFFIT: generate an interrupt when the BUFF_COUNT in DMASTATUSx
– CHANN_ENB: Run and stop at end of buffer
programmed in the AUTO_VALID and SHRT_PCKT fields of EPTCTLx.) (See
Endpoint Control Register” on page 658
reaches 0.
669). Transfer descriptors are chained. Before executing
and
Figure 32-11. Autovalid with
AT32AP7001
DMA)
”USBA DMA
”USBA
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