AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 515

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

28.6.7.3
Figure 28-29. NWAIT Assertion in Write Access: Ready Mode (MODE.EXNWMODE = 3).
32015G–AVR32–09/09
In te rn a lly syn ch ro n ize d
N W A IT s ig n a l
N B S 0 , N B S 1 ,
C L K _ S M C
A 0 , A 1
A [2 5 :2 ]
N W A IT
D [1 5 :0 ]
Ready mode
N C S
N W E
6
In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC
begins the access by down counting the setup and pulse counters of the read/write controlling
signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
28-30 on page
performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure 28-30 on page
4
5
4
3
516. After deassertion, the access is completed: the hold step of the access is
516.
3
2
1
2
E X N W M O D E = 3 (R e a d y m o d e )
W R IT E M O D E = 1 (N W E _ co n tro lle d )
N W E P U L S E = 5
N C S W R P U L S E = 7
W rite cyc le
0
1
F R O Z E N S T A T E
0
1
Figure 28-29 on page 515
0
1
0
AT32AP7001
and
Figure
Fig-
515