AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 780

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

37.4.4
32015G–AVR32–09/09
Service Access Bus
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the
data register path will show the ID-code of the device, since IDCODE is the default JTAG
instruction. It may be desirable to have the AVR32 device in reset during test mode. If not reset,
inputs to the device may be determined by the scan operations, and the internal software may
be in an undetermined state when exiting the test mode. Entering reset, the outputs of any Port
Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If
needed, the BYPASS instruction can be issued to make the shortest possible scan chain
through the device. The device can be set in the reset state either by pulling the external
RESETn pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset
Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the
internal chip clock, which is not required to run.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on
the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
The AVR32 architecture offers a common interface for access to On-Chip Debug, programming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG port through a bus master module, which also handles synchroniza-
tion between the JTAG and SAB clocks.
When accessing the SAB through the TAP there are no limitations on TCK frequency compared
to chip frequency, although there must be an active system clock in order for the SAB accesses
to complete. If the system clock is switched off in sleep mode, activity on the TCK pin will restart
the system clock automatically, without waking the device from sleep. JTAG masters may opti-
mize the transfer rate by adjusting the TCK frequency in relation to the system clock. This ratio
can be measured with the SYNC instruction.
The Service Access Bus uses 36 address bits to address memory or registers in any of the
slaves on the bus. The bus supports accesses of words (32 bits). All accesses must be aligned
to the size of the access, i.e. word accesses must have the two lowest address bits cleared.
A number of private instructions are used to access SAB resources. Each of these are described
in detail in
tion allows a read or write a word to any 36-bit address on the bus. NEXUS_ACCESS instruction
is a Nexus-compliant shorthand instruction for accessing the 32-bit OCD registers in the 7-bit
address space reserved for these. These instructions require two passes through the Shift-DR
TAP state: one for the address and control information, and one for data.
”Private JTAG Instructions” on page
784. The MEMORY_WORD_ACCESS instruc-
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