AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 354

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.7.1.4
24.7.2
32015G–AVR32–09/09
Transmitter Operations
Serial Clock Ratio Considerations
Figure 24-7. Receiver Clock Management
The Transmitter and the Receiver can be programmed to operate with the clock signals provided
on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode
data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:
In addition, the maximum clock speed allowed on the TX_CLOCK pin is:
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (TCMR).
“24.7.4” on page 356.
The frame synchronization is configured setting the Transmit Frame Mode Register (TFMR).
See Section “24.7.5” on page 358.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the TCMR. Data is written by the application to the THR register then
transferred to the shift register according to the data format selected.
When both the THR and the transmit shift register are empty, the status flag TXEMPTY is set in
SR. When the Transmit Holding register is transferred in the Transmit shift register, the status
flag TXRDY is set in SR and additional data can be loaded in the holding register.
Transmitter
RX_CLOCK (pin)
Divider
Clock
Clock
–Master Clock divided by 2 if Receiver Frame Synchro is input
–Master Clock divided by 3 if Receiver Frame Synchro is output
–Master Clock divided by 6 if Transmit Frame Synchro is input
–Master Clock divided by 2 if Transmit Frame Synchro is output
MUX
CKS
CKO
Controller
Tri-state
MUX
INV
CKI
Data Transfer
Controller
Tri-state
AT32AP7001
CKG
See Section
Receiver
Output
Clock
Clock
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