AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 197

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32015G–AVR32–09/09
3. Write the starting destination address in the DARx register for channel x.
Note:
4. Write the channel configuration information into the CFGx register for channel x.
5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are
7. Make sure that the LLI.SARx register location of all LLIs in memory point to the start
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing a
10. Program the CTLx, CFGx registers according to Row 8 as shown in
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note:
14. Source and destination requests single and burst DMACA transactions to transfer the
Note:
15. The DMACA does not wait for the block interrupt to be cleared, but continues and fetches
– vi. Incrementing/decrementing or fixed address for destination DINC field.
a. Designate the handshaking interface type (hardware or software) for the source and
b. If the hardware handshaking interface is activated for the source or destination
shown in Row 8 of
List item must be set as described in Row 1 or Row 5 of
18-7 on page 179
non-zero and point to the next Linked List Item.
source block address proceeding that LLI fetch.
memory is cleared.
‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
180
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
block of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transaction (burst and single) in the block and carry out the block
transfer.
the next LLI from the memory location pointed to by current LLPx register and automati-
cally reprograms the SARx, CTLx and LLPx channel registers. The DARx register is left
unchanged. The DMA transfer continues until the DMACA samples the CTLx and LLPx
registers at the end of a block transfer match that described in Row 1 or Row 5 of
18-1 on page
last block in the DMA transfer.
fetched during an LLI fetch, are not used.
destination peripherals. This is not required for memory. This step requires program-
ming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the
hardware handshaking interface to handle source/destination requests for the spe-
cific channel. Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DEST_PER bits, respectively.
The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. The LLI.DARx register
location of the LLI although fetched is not used. The DARx register in the DMACA remains
unchanged.
The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although
180. The DMACA then knows that the previous block transferred was the
shows a Linked List example with two list items.
Table 18-1 on page
180, while the LLI.CTLx register of the last Linked
Table 18-1 on page
AT32AP7001
Table 18-1 on page
180.
Figure
Table
197