AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 70

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

8.9
32015G–AVR32–09/09
Data Hazards
Data hazards are caused by data dependencies between instructions which are in different
stages of the pipeline and reads/writes registers which are common to several pipeline stages.
Because of the 3-stage pipeline employed in the PICO data hazards might exist between
instructions. Data hazards are handled by hardware interlocks which can stall a new read com-
mand from or write command to the PICO register file.
Table 8-5.
Instruction
picovmul
picovmac
picosvmul
picosvmac
Data Hazards
Next
Instruction
picomv.x Pr,...
picold.x
picoldm
picomv.x Rd,...
picost.x
picostm
Condition
Write-After-Read (WAR) or Write-After-Write (WAW)
Hazard will occur if writing COEFFn_A/B, VMUn_OUT
or CONFIG since these are accessed when the PICO
command is in Pipeline Stage 2 and Pipeline Stage 3.
Writes to INPIXn registers produces no hazard since
they are only accessed in Pipeline Stage 1.
Read-After-Write Hazard (RAW) will occur if reading
the PICO register file while a command is in the
pipeline.
AT32AP7001
Stall
Cycles
1
0
2
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