MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet - Page 8

• Manufacturer Part Number: MT48H8M16LFB4-10
• Description: IC SDRAM 128MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Initialization
Mode Register Definition
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks) are quad-bank DRAMs that oper-
ate at 1.8V and include a synchronous interface (all signals are registered on the positive
edge of the clock signal, CLK). Each of the x16’s 32,554,432-bit banks is organized as
4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (A0–A8) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions and device operation.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Power should be
applied to V
and the clock is stable (stable clock is defined as a signal cycling within timing con-
straints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing
any command other than a COMMAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the end of this period, command
inhibit or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one command inhibit or NOP com-
mand having been applied, a PRECHARGE command should be applied. All banks must
then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO
refresh cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
In order to achieve low power consumption, there are two mode registers in the mobile
component, mode register and extended mode register. The mode register is illustrated
in Figure 4, "Mode Register Definition," on page 11 (the extended mode register is illus-
trated in Figure 6, "Extended Mode Register Diagram," on page 14).
The mode register defines the specific mode of operation of the SDRAM, including burst
length, burst type, CAS latency, operating mode, and write burst mode. The mode regis-
ter is programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10, and M11 should be set to zero.
M12 and M13 should be set to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
DD
and V
DD
Q simultaneously. Once the power is applied to V
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16 Mobile SDRAM
Functional Description
©2003 Micron Technology, Inc. All rights reserved.
DD
and V
DD
Q,