MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet - Page 26

• Manufacturer Part Number: MT48H8M16LFB4-10
• Description: IC SDRAM 128MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 17: WRITE Burst
Figure 18: WRITE-To-WRITE
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Note:
Note:
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a
different bank.
COMMAND
COMMAND
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20 on page 27. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRE-
CHARGE command to the same bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued
which the last desired input data element is registered. The auto precharge mode
requires a
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the PRE-
CHARGE command. An example is shown in Figure 21 on page 28. Data n + 1 is either
the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until
ADDRESS
ADDRESS
BL = 2. DQM is LOW.
DQM is LOW. Each WRITE command may be to any bank.
CLK
CLK
DQ
DQ
t
WR of at least one clock plus time, regardless of frequency.
WRITE
WRITE
BANK,
COL n
BANK,
COL n
D
T0
T0
D
TRANSITIONING DATA
n
IN
n
IN
n + 1
NOP
n + 1
NOP
T1
T1
D
D
IN
IN
DON’T CARE
WRITE
BANK,
COL b
NOP
T2
T2
D
b
IN
26
DON’T CARE
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16 Mobile SDRAM
t
WR after the clock edge at
©2003 Micron Technology, Inc. All rights reserved.
t
RP is met.
READs