MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet - Page 17

• Manufacturer Part Number: MT48H8M16LFB4-10
• Description: IC SDRAM 128MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Auto Precharge
BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst, except
in the full-page burst mode, where auto precharge does not apply. Auto precharge is non
persistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in "Operation" on
page 18.
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST TER-
MINATE command will be truncated, as shown in "Operation" on page 18.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
CHARGE command as shown in "Operation" on page 18.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (
command every 15.625µs will meet the refresh requirement and ensure that each row is
refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the
minimum cycle rate (
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down, as long as power is not completely removed from the
SDRAM. When in the self refresh mode, the SDRAM retains data without external clock-
ing. The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs
to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to
indefinite period beyond that.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
t
RFC), once every 64ms.
17
t
RAS and may remain in self refresh mode for an
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF). Providing a distributed AUTO REFRESH
t
RP has been met after the PRE-
128Mb: x16 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
BURST TERMINATE