MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet - Page 32

• Manufacturer Part Number: MT48H8M16LFB4-10
• Description: IC SDRAM 128MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Concurrent Auto Precharge
READ with Auto Precharge
Figure 27: READ With Auto Precharge Interrupted by a READ
Figure 28: READ With Auto Precharge Interrupted by a WRITE
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Note:
Note:
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
Micron SDRAM devices support concurrent auto precharge, which allows an access
command (READ or WRITE) to another bank while an access command with auto pre-
charge enabled is executing. Four cases where concurrent auto precharge occurs are
defined below.
Internal
States
Internal
States
rupt a READ on bank n, 2 or 3 clocks later, depending on CAS latency. The precharge
to bank n will begin when the READ to bank m is registered (Figure 27).
registers, a READ on bank n will be interrupted. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 28).
DQM is LOW.
DQM is HIGH at T2 to prevent D
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
1
Active
Page
READ - AP
BANK n,
BANK n
COL a
T0
Page Active
T0
NOP
READ with Burst of 4
READ - AP
Page Active
BANK n,
Page Active
T1
NOP
BANK n
COL a
T1
CL = 3 (BANK n)
READ with Burst of 4
CAS Latency = 3 (BANK n)
T2
NOP
32
T2
NOP
OUT
T3
READ - AP
BANK m,
D
T3
NOP
BANK m
COL d
OUT
a
-a+1 from contending with D
Interrupt Burst, Precharge
READ with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
T4
IN
Interrupt Burst, Precharge
CL = 3 (BANK m)
NOP
WRITE with Burst of 4
D
OUT
a
t
RP - BANK n
T5
d + 1
NOP
T5
D
IN
NOP
D
a + 1
t
RP - BANK n
OUT
128Mb: x16 Mobile SDRAM
T6
d + 2
NOP
D
T6
IN
NOP
D
OUT
d
DON’T CARE
DON’T CARE
T7
t WR - BANK m
d + 3
NOP
Idle
D
IN
T7
Write-Back
NOP
©2003 Micron Technology, Inc. All rights reserved.
t RP - BANK m
Precharge
D
d + 1
Idle
OUT
IN
-d at T4.
Power-Down